Packaged Semiconductor Devices and Methods of Packaging Semiconductor Devices

ABSTRACT

Packaged semiconductor devices and methods of packaging semiconductor devices are disclosed. In some embodiments, a method of packaging a semiconductor device includes forming a mask coating over a carrier, coupling an integrated circuit die over the mask coating, and disposing a molding compound around the integrated circuit die. The method includes forming an interconnect structure over the integrated circuit die and the molding compound.

PRIORITY CLAIM AND CROSS-REFERENCE

This application is a continuation of U.S. patent application Ser. No.15/062,757, filed on Mar. 7, 2016, and entitled “Packaged SemiconductorDevices and Methods of Packaging Semiconductor Devices,” which is adivisional of U.S. patent application Ser. No. 14/182,574, filed on Feb.18, 2014, now U.S. Pat. No. 9,299,688, issued Mar. 29, 2016, andentitled “Packaged Semiconductor Devices and Methods of PackagingSemiconductor Devices,” which claims priority to U.S. ProvisionalApplication Ser. No. 61/914,264, filed on Dec. 10, 2013, entitled“Molding Mask Structure for Wafer Level Package,” which applications arehereby incorporated herein by reference.

BACKGROUND

Semiconductor devices are used in a variety of electronic applications,such as personal computers, cell phones, digital cameras, and otherelectronic equipment, as examples. Semiconductor devices are typicallyfabricated by sequentially depositing insulating or dielectric layers,conductive layers, and semiconductive layers of material over asemiconductor substrate, and patterning the various material layersusing lithography to form circuit components and elements thereon.

Dozens or hundreds of integrated circuits are typically manufactured ona single semiconductor wafer. The individual dies are singulated bysawing the integrated circuits along a scribe line. The individual diesare then packaged separately, in multi-chip modules, or in other typesof packaging, as examples.

The semiconductor industry continues to improve the integration densityof various electronic components (e.g., transistors, diodes, resistors,capacitors, etc.) by continual reductions in minimum feature size, whichallow more components to be integrated into a given area. These smallerelectronic components also require smaller packages that utilize lessarea than packages of the past, in some applications.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the followingdetailed description when read with the accompanying figures. It isnoted that, in accordance with the standard practice in the industry,various features are not drawn to scale. In fact, the dimensions of thevarious features may be arbitrarily increased or reduced for clarity ofdiscussion.

FIGS. 1 through 9 and 16 illustrate cross-sectional views of a method ofpackaging semiconductor devices at various stages in accordance withsome embodiments.

FIG. 10 is a cross-sectional view illustrating a packaged semiconductordevice in accordance with some embodiments.

FIG. 11 is a cross-sectional view illustrating a packaged semiconductordevice in accordance with other embodiments.

FIG. 12 is a cross-sectional view illustrating a packaged semiconductordevice in accordance with some embodiments.

FIG. 13 is a more detailed view of a portion of the packagedsemiconductor device shown in FIG. 12 in accordance with someembodiments.

FIG. 14 is a cross-sectional view illustrating a packaged semiconductordevice in accordance with some embodiments.

FIG. 15 is a flow chart of a method of packaging semiconductor devicesin accordance with some embodiments.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, orexamples, for implementing different features of the provided subjectmatter. Specific examples of components and arrangements are describedbelow to simplify the present disclosure. These are, of course, merelyexamples and are not intended to be limiting. For example, the formationof a first feature over or on a second feature in the description thatfollows may include embodiments in which the first and second featuresare formed in direct contact, and may also include embodiments in whichadditional features may be formed between the first and second features,such that the first and second features may not be in direct contact. Inaddition, the present disclosure may repeat reference numerals and/orletters in the various examples. This repetition is for the purpose ofsimplicity and clarity and does not in itself dictate a relationshipbetween the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,”“above,” “upper” and the like, may be used herein for ease ofdescription to describe one element or feature's relationship to anotherelement(s) or feature(s) as illustrated in the figures. The spatiallyrelative terms are intended to encompass different orientations of thedevice in use or operation in addition to the orientation depicted inthe figures. The apparatus may be otherwise oriented (rotated 90 degreesor at other orientations) and the spatially relative descriptors usedherein may likewise be interpreted accordingly.

Some embodiments of the present disclosure provide novel methods andstructures for packaging semiconductor devices. Molding mask structuresfor wafer level packages and packaging methods are described herein. Anovel mask coating is included in the packaged semiconductor devices.The mask coating is laminated on a temperate bond layer and increasesfluidity of molding compound materials also included in the packagedsemiconductor devices, eliminating or at least ameliorating voidformation issues.

FIGS. 1 through 9 illustrate cross-sectional views of a method ofpackaging semiconductor devices at various stages in accordance withsome embodiments. Referring first to FIG. 1, a carrier 100 is provided.The carrier 100 may comprise a wafer such as a semiconductor wafer, orthe carrier 100 may comprise an organic substrate or other types ofsubstrates. The carrier 100 comprises a sacrificial component that willbe removed after one or more integrated circuit dies are packaged, suchas integrated circuit dies 106 shown in FIG. 3, to be described furtherherein. The carrier 100 may later be cleaned and used to package othersemiconductor devices, for example. Alternatively, the carrier 100 maybe discarded after the packaging process.

A temperate bond layer 102 is formed on the carrier 100. The temperatebond layer 102 comprises a temporary bond layer that is coated on a topsurface of the carrier 100 in some embodiments. The temperate bond layer102 comprises about 1 μm to about 10 μm of a light to heat conversion(LTHC) material, for example. The temperate bond layer 102 may be formedusing a deposition process, a spin coating process, or a printingprocess, as examples. Alternatively, the temperate bond layer 102 maycomprise other materials, dimensions, and formation methods. In someembodiments, the temperate bond layer 102 is not included.

A mask coating 104 is formed over the carrier 100, e.g., over thetemperate bond layer 102 disposed on the carrier 100, as shown in FIG.2. The mask coating 104 may be formed using a deposition process, a spincoating process, or a printing process, as examples. In someembodiments, the mask coating 104 comprises a functional group of amaterial such as methylolpmpanel hmylate, 2-hydroxyethyl methacrylate,and/or combinations or multiple layers thereof, for example. In someembodiments, the mask coating 104 may include methylolpmpanel hmylate,i.e., CAS Registry Number: 15625-845 (CAS Registry Number is aRegistered Trademark of the American Chemical Society), for example. Insome embodiments, the mask coating 104 may include 2-hydroxyethylmethacrylate, i.e., CAS Registry Number: 868-77-9 (CAS Registry Numberis a Registered Trademark of the American Chemical Society), forexample. The mask coating 104 comprises a thickness of about 10 μm toabout 40 μm in some embodiments. The mask coating 104 comprises amaterial that is curable at a temperature of about 100° C. to about 175°C. over a time period of about 1 hour to about 3 hours in someembodiments. Alternatively, the mask coating 104 may comprise othermaterials, dimensions, formation methods, and curing temperature andtimes.

An integrated circuit die 106 is coupled over the mask coating 104, asshown in FIG. 3. In some embodiments, a single integrated circuit die106 is coupled over the mask coating 104 (not shown). In otherembodiments, a plurality of integrated circuit dies 106 are coupled overthe mask coating 104. Integrated circuit dies 106 may be packagedindividually, or two or more integrated circuit dies 106 may be packagedtogether, in accordance with some embodiments of the present disclosure,for example.

Each of the integrated circuit dies 106 may include a workpiece 110. Theworkpiece 110 may include a semiconductor substrate comprising siliconor other semiconductor materials and may be covered by an insulatinglayer, for example. The workpiece 110 may also include other activecomponents or circuits, not shown. The workpiece 110 may comprisesilicon oxide over single-crystal silicon, for example. The workpiece110 may conductive layers or semiconductor elements, e.g., transistors,diodes, etc. Compound semiconductors, GaAs, InP, Si/Ge, or SiC, asexamples, may be used in place of silicon. The workpiece 110 maycomprise a silicon-on-insulator (SOI) or a germanium-on-insulator (GOI)substrate, as examples.

The integrated circuit dies 106 may include a plurality of connectorssuch as contact pads 114 disposed on a surface thereof. The contact pads114 may comprise Cu, Al, other metals, or alloys, combinations, ormultiple layers thereof, for example. The contact pads 114 may bedisposed within an insulating material 116 which may comprise siliconnitride, silicon dioxide, other insulators or polymers, or combinationsor multiple layers thereof, for example. The contact pads 114 may becoupled to internal wiring of the integrated circuit dies 106, such asto vias and/or conductive lines in metallization layers or polysiliconlayers of the integrated circuit dies 106, as examples, not shown.

In some embodiments, the integrated circuit dies 106 include a dieattach film (DAF) 112 formed thereon. The DAF 112 may comprise a glue,an adhesive, or an adhesive film that is adapted to adhere theintegrated circuit dies 106 to the mask coating 104 disposed over thecarrier 100 in some embodiments, for example. The integrated circuitdies 106 may be attached over the carrier 100 (e.g., over the maskcoating 104 disposed over the carrier 100) using a pick-and-placemachine, other mechanism, or manually, for example.

The mask coating 104 comprises a mask that is interjacent the DAF 112and the temperate bond layer 102 in some embodiments, for example. Themask coating 104 is disposed between the DAF 112 and the temperaturebond layer 102 in some embodiments, for example.

A molding compound 120 is disposed around the integrated circuit dies106 over the mask coating 104, as shown in FIG. 4. The molding compound120 fills spaces between the dies 106 and encapsulates the dies 106, forexample. The molding compound 120 comprises a molding material and maycomprise epoxy, an organic polymer, or a polymer with or without asilica-based or glass filler added, as examples. In some embodiments,the molding compound 120 comprises a liquid molding compound (LMC) thatis a gel type liquid when applied. Alternatively, the molding compound120 may comprise other insulating materials. If the molding compound 120extends over a top surface of contact pads 114 of the integrated circuitdies 106, the molding compound 120 is removed from over the contact pads114 using a chemical-mechanical polish (CMP), etch process, or othermethods in some embodiments, for example. The molding compound 120 isformed around the integrated circuit dies 106 in some embodiments.

An interconnect structure 122 is formed over the integrated circuit dies106 and the molding compound 120, as shown in FIG. 5. The interconnectstructure 122 includes a plurality of insulating material layers 124 anda plurality of conductive lines 126 and a plurality of conductive vias128 formed within the insulating material layers 124. The insulatingmaterial layers 124 may comprise polybenzoxazole (PBO) or otherinsulators, and the conductive lines 126 and vias 128 may comprise Cu,Al, other metals, or alloys or multiple layers thereof, in someembodiments, as examples. The interconnect structure 122 is disposedover the integrated circuit dies 106 and the molding compound 120, forexample. The interconnect structure 122 may include a plurality ofcontact pads 130 formed proximate a surface thereof. The contact pads130 may comprise ball grid array (BGA) ball mounts in some embodiments,for example.

In some embodiments, the interconnect structure 122 may comprise aredistribution layer (RDL) or a post-passivation interconnect (PPI)structure, for example. In some embodiments, the interconnect structure122 comprises horizontal electrical connections for the packagedsemiconductor device (see packaged semiconductor device 140 shown inFIG. 9), for example. Alternatively, the interconnect structure 122 maycomprise other types of electrical connection structures.

In some embodiments, a plurality of conductors 132 are coupled to theinterconnect structure 122, as shown in FIG. 6. The plurality ofconductors 132 are coupled to portions of the interconnect structure 122in some embodiments, for example. The plurality of conductors 132 may becoupled to the contact pads 130 of the interconnect structure 122 insome embodiments, as shown in FIG. 6. The conductors 132 are formed overand are coupled to portions of the horizontal electrical connections ofthe interconnect structure 122 in some embodiments, for example.

The conductors 132 may comprise a eutectic material such as solder thatis coupled to contact pads 130 or bond pads of the interconnectstructure 122, for example. The conductors 132 may each comprise asolder bump or a solder ball, as examples. The conductors 132 mayfunction as electrical connectors for the packaged semiconductor device.The eutectic material of the conductors 132 may be re-flowed toelectrically and mechanically connect the packaged semiconductor deviceto another device or object, for example.

The use of the word “solder” herein includes both lead-based andlead-free solders, such as Pb—Sn compositions for lead-based solder;lead-free solders including InSb; tin, silver, and copper (“SAC”)compositions; and other eutectic materials that have a common meltingpoint and form conductive solder connections in electrical applications.For lead-free solder, SAC solders of varying compositions may be used,such as SAC 105 (Sn 98.5%, Ag 1.0%, Cu 0.5%), SAC 305, and SAC 405, asexamples. Lead-free conductors 132 such as solder balls may be formedfrom SnCu compounds as well, without the use of silver (Ag).Alternatively, lead-free solder connectors may include tin and silver,Sn—Ag, without the use of copper. The conductors 132 may be one among anarray of the conductors 132 formed as a grid, referred to as a “ballgrid array” or “BGA”. The conductors 132 may alternatively be arrangedin other shapes. The conductors 132 may also comprise non-sphericalconductive connectors, for example. In some embodiments, the conductors132 are not included.

The molding compound 120 is also referred to herein as a first moldingcompound 120. In some embodiments, a second molding compound 134 isdisposed around the plurality of conductors 132, as shown in FIG. 6. Thesecond molding compound 134 may comprise similar materials described forthe first molding compound 120, for example. In some embodiments, thesecond molding compound 134 comprises an LMC. In some embodiments, thesecond molding compound 134 is not included.

In some embodiments, the carrier 100 is then removed, as shown in FIG.7. In some embodiments, the temperate bond layer 102 is also removed,also shown in FIG. 7. The back side of the packaged semiconductor devicemay be thinned using a CMP or grinding process to remove the temperatebond layer 102 in some embodiments, for example. The temperate bondlayer 102 may be removed using an etch process in some embodiments. Inother embodiments, the temperate bond layer 102 may be left remaining inthe structure.

In some embodiments, the mask coating 104 may also be removed. In otherembodiments, the mask coating 104 is left remaining in the structure.The mask coating 104 may be removed when the temperate bond layer isremoved or using an additional process step, for example. FIG. 16illustrates an embodiment wherein mask coating 104 is removed.

Next, the interconnect structure 122, the molding compounds 120 and 134,and the mask coating 104 are singulated using a die saw 138, laser, orother device to form a plurality of packaged semiconductor devices 140,each of the plurality of packaged semiconductor devices 140 including atleast one of the plurality of integrated circuit dies 106, as shown inFIG. 8. In some embodiments, the packaged semiconductor devices 140 maybe attached to a dicing tape 136 before the singulation process, alsoshown in FIG. 8. The dicing tape 136 is then removed, leaving thepackaged semiconductor device 140 shown in FIG. 9.

The packaged semiconductor device 140 includes at least one integratedcircuit die 106. In some embodiments, the packaged semiconductor device140 includes two or more integrated circuit dies 106, for example. Theintegrated circuit dies 106 packaged together in the packagedsemiconductor device 140 may comprise similar, the same, or differentfunctions, for example. The molding compound 120 is disposed around theintegrated circuit die or dies 106, and the mask coating 104 is disposedover a first side of the integrated circuit die or dies 106 and themolding compound 120 (e.g., the top side in the view shown in FIG. 9).The interconnect structure 122 is disposed over a second side of theintegrated circuit die or dies 106 and the molding compound 120 (e.g.,the bottom side in the view shown in FIG. 9). The second side isopposite the first side of the integrated circuit die or dies 106 andthe molding compound 120.

In some embodiments, a lid, a heat spreader, or a backside protectivefilm 142 is disposed over the mask coating 104, as shown in FIG. 9. Thelid, heat spreader, or backside protective film 142 may be disposed overthe molding compound 120 and the integrated circuit dies 106 inembodiments wherein the mask coating 104 is removed, as another example.The lid or heat spreader 142 may comprise copper or aluminum comprisinga thickness of about 100 μm to about 500 μm, as examples. The protectivefilm 142 may comprise about 10 μm to about 100 μm of epoxy or a polymer,as examples. The lid, heat spreader, or backside protective film 142 maybe attached using an adhesive or formed using a deposition or coatingprocess, for example. Alternatively, a lid, heat spreader, or backsideprotective film 142 may not be included.

In some embodiments, the plurality of conductors 132 are coupled to asubstrate 144, as shown in FIG. 10. The substrate 144 may comprise aprinted circuit board (PCB) in some embodiments. Alternatively, thesubstrate 144 may comprise other materials, such as an interposer,another integrated circuit die, or other objects, as example. In someembodiments, the second molding compound 134 is not included, alsoillustrated in FIG. 10. The packaged semiconductor device 150 includesthe packaged semiconductor device 140 that is coupled to the substrate144.

In some embodiments, an underfill material 146 may be disposed betweenthe plurality of conductors 132 and between the substrate 144 and theinterconnect structure 122, also illustrated in FIG. 10. The underfillmaterial 146 may comprise an epoxy material, an organic polymer, orother materials. The underfill material 146 may include a filler such assilica, aluminum oxide, or other filler materials, as example. Theunderfill material 146 may be applied using a needle along one or moresides of the packaged semiconductor device 150 or through an apertureformed within the molding compound 120, interconnect structure 122, andmask coating 104, for example, not shown.

In some embodiments, the second molding compound 134 is included, and anunderfill material 146 is also included in the packaged semiconductordevice 150, as shown in FIG. 11. The second molding compound 134 may bedisposed between the plurality of conductors 132 and between theunderfill material 146 and the interconnect structure 122, for example.

FIG. 12 is a cross-sectional view illustrating a packaged semiconductordevice 150 in accordance with some embodiments, wherein the lid, heatspreader, or backside protective film 142 is included and wherein theconductors 132 are coupled to a substrate 144. Advantageously, becauseof the inclusion of the mask coating 104, the application of the moldingcompound 120 is improved, as shown in a more detailed view in FIG. 13,which is a more detailed view of a portion of the packaged semiconductordevice 150 shown in FIG. 12 in accordance with some embodiments. In someembodiments, the molding compound 120 includes a filler comprising glassspheres 152. Advantageously, grinding processes used in the packagingprocesses are prevented from deleteriously affecting the fillermaterials of the molding compound 120, because of the inclusion of themask coating 104 in accordance with some embodiments of the presentdisclosure, for example.

FIG. 14 is a cross-sectional view illustrating a packaged semiconductordevice 160 in accordance with some embodiments. The packagedsemiconductor device 160 comprises a package-on-a package (PoP) devicein accordance with some embodiments. The PoP device 160 includes apackaged semiconductor device 150 described herein that is coupled to apackaged semiconductor device 170. The packaged semiconductor device 150comprises a first packaged semiconductor device, and the packagedsemiconductor device 170 comprises a second packaged semiconductordevice that is coupled to the packaged semiconductor device 150 inaccordance with some embodiments, for example.

The packaged semiconductor device 150 includes a plurality ofthrough-vias 162 formed within the molding compound 120. Thethrough-vias 162 provide vertical connections for the packagedsemiconductor device 150. Contact pads 164 are coupled to thethrough-vias 162. The contact pads 164 may be formed over or within themask coating 104, as illustrated in FIG. 14. The contact pads 164 of thepackaged semiconductor device 150 are coupled to contact pads (notshown) of packaged semiconductor device 170 by conductors 178 which maycomprise solder balls or other materials (similar to the materialsdescribed for conductors 132).

Packaged semiconductor device 170 includes one or more integratedcircuit dies 176 coupled to a substrate 174. Wire bonds 172 may becoupled to contact pads on a top surface of the integrated circuit dieor dies 176, which are coupled to bond pads (not shown) on the substrate174. A molding compound 168 may be disposed over the wire bonds 172,integrated circuit die or dies 176, and the substrate 174.

Alternatively, a PoP device 160 may include two packaged semiconductordevices 150 described herein that are coupled together in someembodiments, not shown in the drawings. In some embodiments, the PoPdevice 160 may comprise a system-on-a-chip (SOC) device, as anotherexample.

FIG. 15 is a flow chart 180 of a method of packaging semiconductordevices in accordance with some embodiments. In step 182, a mask coating104 (see also FIG. 2) is formed over a carrier 100. In step 184, anintegrated circuit die 106 is coupled over the mask coating 104 (FIG.3). In step 186, a molding compound 120 is disposed around theintegrated circuit die 106 (FIG. 4). In step 188, an interconnectstructure 122 is formed over the integrated circuit die 106 and themolding compound 120 (FIG. 5).

Advantages of some embodiments of the present disclosure includeproviding a novel mask coating 104 that decreases friction force betweenmolding compound 120 materials and a carrier 100. The molding compound120 flows more smoothly when applied, eliminating or at leastameliorating void formation issues in the molding compound 120, in someembodiments. Increased packaging yields are achievable by implementingembodiments of the present disclosure. Furthermore, the novel packagedsemiconductor devices and methods are easily implementable intopackaging process flows.

In some embodiments, a method of packaging a semiconductor deviceincludes forming a mask coating over a carrier, coupling an integratedcircuit die over the mask coating, and disposing a molding compoundaround the integrated circuit die. The method includes forming aninterconnect structure over the integrated circuit die and the moldingcompound.

In other embodiments, a method of packaging semiconductor devicesincludes forming a temperate bond layer over a carrier, forming a maskcoating over the temperate bond layer, and coupling a plurality ofintegrated circuit dies over the mask coating. The method includesdisposing a molding compound around the plurality of integrated circuitdies, forming an interconnect structure over the plurality of integratedcircuit dies and the molding compound, and removing the carrier.

In yet other embodiments, a packaged semiconductor device includes anintegrated circuit die, a molding compound disposed around theintegrated circuit die, and a mask coating disposed over a first side ofthe integrated circuit die and the molding compound. An interconnectstructure is disposed over a second side of the integrated circuit dieand the molding compound, wherein the second side is opposite the firstside.

In some aspects, embodiments described herein may provide for a packagedsemiconductor device, comprising an integrated circuit die, and amolding compound disposed around the integrated circuit die. Thepackaged semiconductor device also includes a mask coating disposed overa first side of the integrated circuit die and the molding compound, andan interconnect structure disposed over a second side of the integratedcircuit die and the molding compound, wherein the second side isopposite the first side.

In other aspects, embodiments described herein may provide for apackage-on-package (PoP) device, comprising a mask coating, and one ormore integrated circuit (IC) dies on the mask coating. The PoP devicefurther includes a first molding compound at least partiallyencapsulating the one or more IC dies and contacting the mask coating,an interconnect structure over the one or more IC dies and the firstmolding compound, and a second semiconductor device coupled to aplurality of contact pads disposed over or within the mask coating ofthe first semiconductor device.

In yet other aspects, embodiments described herein may provide for adevice, comprising an integrated circuit (IC) die at least partiallyencapsulated by a molding compound, a mask coating overlying a firstside of the IC die and the molding compound, wherein the mask coatingcomprises a functional group of a material selected from the groupconsisting essentially of methylolpmpanel hmylate, 2-hydroxyethylmethacrylate, and combinations thereof. The device further includes aninterconnect structure electrically connected to contact pads on asecond side of the IC die, the second side being opposite the firstside, and a connector structure electrically connected to theinterconnect structure.

In yet other aspects, embodiments described herein may provide for amethod including reducing a friction force between a carrier and a firstmolding compound, attaching an integrated circuit die over the carrier,encapsulating the integrated circuit die in the first molding compound,the first molding compound extending along a sidewall of the integratedcircuit die. The method further includes forming an interconnectstructure over the integrated circuit die and the first moldingcompound, the integrated circuit die being interposed between thecarrier and the interconnect structure.

In yet other aspects, embodiments described herein may provide for amethod including forming a mask coating over a carrier, the mask coatingreducing a friction force between the carrier and a first moldingcompound, and attaching an integrated circuit die to the mask coatingusing an adhesive film. The method further includes forming the firstmolding compound around the integrated circuit die, and forming aninterconnect structure in electrical contact with the integrated circuitdie, the integrated circuit die being interposed between the maskcoating and the interconnect structure.

In yet other aspects, embodiments described herein may provide for adevice including a friction-reducing mask coating, a first moldingcompound over the friction-reducing mask coating, and an integratedcircuit die extending into the first molding compound. The devicefurther includes an adhesive film between the integrated circuit die andthe friction-reducing mask coating, an interconnect structure over theintegrated circuit die and the first molding compound, and a secondmolding compound over the interconnect structure.

The foregoing outlines features of several embodiments so that thoseskilled in the art may better understand the aspects of the presentdisclosure. Those skilled in the art should appreciate that they mayreadily use the present disclosure as a basis for designing or modifyingother processes and structures for carrying out the same purposes and/orachieving the same advantages of the embodiments introduced herein.Those skilled in the art should also realize that such equivalentconstructions do not depart from the spirit and scope of the presentdisclosure, and that they may make various changes, substitutions, andalterations herein without departing from the spirit and scope of thepresent disclosure.

What is claimed is:
 1. A method comprising: reducing a friction forcebetween a carrier and a first molding compound; attaching an integratedcircuit die over the carrier; encapsulating the integrated circuit diein the first molding compound, the first molding compound extendingalong a sidewall of the integrated circuit die; and forming aninterconnect structure over the integrated circuit die and the firstmolding compound, the integrated circuit die being interposed betweenthe carrier and the interconnect structure.
 2. The method of claim 1,wherein reducing the friction force between the carrier and the firstmolding compound comprises forming a mask coating over the carrier. 3.The method of claim 2, wherein the mask coating comprises a functionalgroup of a material selected from the group consisting essentially ofmethylolpmpanel hmylate and 2-hydroxyethyl methacrylate.
 4. The methodof claim 2, wherein the mask coating comprises a material that iscurable at a temperature of about 100° C. to about 175° C. over a timeperiod of about 1 hour to about 3 hours.
 5. The method of claim 2,further comprising, before forming the mask coating over the carrier,forming a temperate bond layer over the carrier.
 6. The method of claim1, further comprising attaching a plurality of connectors to theinterconnect structure.
 7. The method of claim 6, further comprisingencapsulating the plurality of connectors in a second molding compound.8. A method comprising: forming a mask coating over a carrier, the maskcoating reducing a friction force between the carrier and a firstmolding compound; attaching an integrated circuit die to the maskcoating using an adhesive film; forming the first molding compoundaround the integrated circuit die; and forming an interconnect structurein electrical contact with the integrated circuit die, the integratedcircuit die being interposed between the mask coating and theinterconnect structure.
 9. The method of claim 8, further comprising,before forming the mask coating over the carrier, forming a temperatebond layer over the carrier.
 10. The method of claim 8, furthercomprising forming a plurality of connectors over the interconnectstructure, the plurality of connectors being electrically coupled to theinterconnect structure.
 11. The method of claim 10, further comprisingforming a second molding compound over the interconnect structure, theplurality of connectors being partially embedded into the second moldingcompound.
 12. The method of claim 11, further comprising, after formingthe second molding compound, removing the carrier.
 13. The method ofclaim 12, further comprising, after removing the carrier, removing themask coating.
 14. The method of claim 12, further comprising, afterremoving the carrier, attaching a heat spreader to the mask coating. 15.A device comprising: a friction-reducing mask coating; a first moldingcompound over the friction-reducing mask coating; an integrated circuitdie extending into the first molding compound; an adhesive film betweenthe integrated circuit die and the friction-reducing mask coating; aninterconnect structure over the integrated circuit die and the firstmolding compound; and a second molding compound over the interconnectstructure.
 16. The device of claim 15, further comprising a plurality ofconductive connectors extending through the second molding compound andcoupled to the interconnect structure.
 17. The device of claim 15,further comprising a heat spreader abutting the friction-reducing maskcoating, the friction-reducing mask coating being interposed between theheat spreader and the integrated circuit die.
 18. The device of claim15, wherein the interconnect structure is electrically coupled to theintegrated circuit die.
 19. The device of claim 15, wherein thefriction-reducing mask coating has a thickness of about 10 μm to about40 μm.
 20. The device of claim 15, wherein the friction-reducing maskcoating comprises a functional group of a material selected from thegroup consisting essentially of methylolpmpanel hmylate and2-hydroxyethyl methacrylate.